The invention relates generally to semiconductor device fabrication and, in particular, to device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating and operating a silicon controlled rectifier.
Complementary metal-oxide-semiconductor (CMOS) technologies integrate p-channel and n-channel field-effect transistors to form an integrated circuit on a single semiconductor substrate. Latch-up, which is precipitated by unwanted transistor action of parasitic bipolar transistors inherently present in bulk CMOS devices, may be a significant issue for bulk CMOS technologies. The unwanted parasitic transistor action, which has various triggers, may cause failure of bulk CMOS devices.
Chips with CMOS devices may be also exposed to electrostatic discharge (ESD) events leading to potentially large and damaging currents within the integrated circuit. Increasing integration densities and performance demands have resulted in reduced device dimensions, which has increased the susceptibility of integrated circuits to ESD events. Manufacturers, assemblers, and users of integrated circuits must take precautions to avoid unintentionally causing ESD events. For example, ESD prevention can be incorporated into the integrated circuit and may include special design techniques for I/O pins and pads, as well as supply pads, to prevent damage to the chip during handling between the time that the chip is manufactured until the time that the chip is installed on a circuit board and while the chip is installed on the circuit board. In the absence of an ESD event, the ESD protection device is in a non-conductive state and is electrically isolated from the protected integrated circuit. If an ESD event is detected, the protection device changes to a conductive state to direct the current of an ESD event to ground and away from the sensitive internal circuits of the chip. The conductive state is maintained until the voltage is discharged to a safe level.
Conventional bulk CMOS devices are susceptible to latch-up. For example, a typical CMOS inverter fabricated using a p-type substrate includes opposite conductivity n- and p-wells that adjoin across a well junction. A p-channel field-effect transistor (pFET) may be fabricated using the n-well and, similarly, an n-channel transistor (nFET) may be fabricated using the p-well. The pFET inherently includes a parasitic p-n-p bipolar junction transistor (BJT) formed by a p-type diffusion, the n-well in which the p-type diffusion is housed, and the p-type substrate. The nFET inherently includes a parasitic n-p-n BJT formed by an n-type diffusion, the p-type substrate, and the n-well housing the corresponding pFET device. The proximity of the nFET to the n-well facilitates the interaction of the BJTs to create a cross-coupled structure. The collector node (i.e., p-type substrate) of the p-n-p BJT serves as the base of the n-p-n BJT, while the collector (i.e., the n-well diffusion) of the n-p-n BJT serves as the base of the p-n-p BJT. The forward-biasing of one parasitic transistor can lead to the forward-biasing of the other parasitic transistor and, if certain conditions are satisfied, latch-up can occur where the p-n junctions of the inverter becomes freely conducting.
A silicon controlled rectifier (SCR) can be constructed with planned wiring of a pFET and an nFET. An SCR, which offer both low capacitance and high failure currents, is a type of ESD device that may be constructed in CMOS technologies to provide ESD protection in CMOS applications that include inverters or other logic gates. SCR devices used for ESD protection are characterized by a trigger voltage/current and a holding voltage/current that determine the device response and effectiveness during an ESD event.
Improved device structures, fabrication and operating methods, and design structures are needed for a silicon controlled rectifier.